The shrinking of metal oxide semiconductor field effect transistor (MOSFET) dimensions for high density, low power and enhanced performance requires reduced power supply voltages. As a result, dielectric thickness and channel length of the transistors are scaled with power supply voltage.
A static random access memory (SRAM) is a significant memory device due to its high speed, low power consumption, and simple operation. Unlike a dynamic random access memory (DRAM) cell, the SRAM does not need to regularly refresh the stored data and it has a straightforward design. However, SRAM stability is severely impacted by scaling. Small mismatches in the devices during processing can cause the cell to favor one of the states, either a ‘1’ or a ‘0’. Mismatches can result from dislocations between the drain and the source or from dopant implantation or thermal anneal temperature fluctuation.
The SRAM cell stability determines the soft-error and the sensitivity of the memory cell to variations in process and operating conditions. One important parameter for the stability is called “gamma ratio”, which is the ratio between the pass-gate nFET ion current and the pull-up pFET ion current.
Stress engineering has been used to improve device performance of FET devices. In particular, stressed liners have been used in recent technologies to improve the device performance. A stressed liner can improve only one type (n-type or p-type) of device, while degrading performance of the other type of device. For example, tensile stress liners are employed for n-type FET device performance improvement, yet the same degrades the device performance of p-type FETs. Similarly, compressive stress liners are employed for p-type FETs device performance improvement, yet the same degrades the device performance of n-type FETs.
Dual stress liner technology in which both compressive and tensile stress liners are present or a relaxation implantation (usually compressive for pFET and relaxation for nFET) have been used in the prior art to avoid the degradation.
Despite the above schemes, the SRAM device stability is degraded because of the following: (i) stress liner uniformity in the SRAM region, and (ii) other process variations such as, for example, contact area size and relaxation boundary variation ( or tensile and compressive nitride boundary) which can cause the stain variation in the device and therefore the Ion variation for the devices.
As the SRAM dimensions scale down, enhanced SRAM device performance is required in order to obtain good SRAM stability and writability.
In view of the above, there is a need for obtaining SRAM cells wherein the overall device performance is enhanced such that the SRAM has improved stability and writability.